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[Embeded-SCM Developuip-0.9

Description: 8051 C/C++ TCP/IP 通信協定源碼-8051 C/C++ TCP/IP communications protocol source code
Platform: | Size: 927744 | Author: titan | Hits:

[TCP/IP stackOpenTCP_8052

Description: 8051 TCP/IP 协议栈 采用 cs8900芯片-Macro to access external data memory area, where CS8900A is connected
Platform: | Size: 68608 | Author: HuangBingWen | Hits:

[VHDL-FPGA-VerilogygyTest

Description: 利用开源网站上的8051核,在Spartan 3A开发板上实现成功,开发环境是Xilinx ISE Design Suite 12.3,顶层文件基于原理图开发,扩展了外部ROM和RAM,且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
Platform: | Size: 18179072 | Author: 杜春城 | Hits:

[VHDL-FPGA-Verilog8051IP

Description: 基于FPGA的8051单片机的IP核应用与设计。-The IP core is based on FPGA for 8051 single chip.
Platform: | Size: 703488 | Author: super | Hits:

[VHDL-FPGA-Verilog6_Sets_of_8051_VHDL_Verilog

Description: it has 6 packages of 8051 sources,including source code(VHDL and Verilog),dc scripts, pdfs, netlists etc. and a MIPS IP package
Platform: | Size: 1198080 | Author: zy | Hits:

[Com Port51

Description: 完整的8051的IP核,用VHDL语言描述-the ip core of c8051,described in VHDL language
Platform: | Size: 758784 | Author: lvpw | Hits:

[Software Engineeringproduct_overview00

Description: esignWare是SoC/ASIC设计者最钟爱的设计IP库和验证IP库。它包括一个独立于工艺的、经验证的、可综合的虚拟微架构的元件集合,包括逻辑、算术、存储和专用元件系列,超过140个模块。DesignWare和 Design Compiler的结合可以极大地改进综合的结果,并缩短设计周期。Synopsys在DesignWare中还融合了更复杂的商业IP(无需额外付费)目前已有:8051微控制器、PCI、PCI-X、USB2.0、MemoryBIST、AMBA SoC结构仿真、AMBA总线控制器等IP模块。-esignWare is SoC/ASIC designers favorite library design IP and verification IP library. It includes a process-independent, proven, and can be integrated set of virtual micro-architecture components, including logic, arithmetic, storage, and special elements series, more than 140 modules. Design Compiler and DesignWare combination can greatly improve the results of a comprehensive and shorten the design cycle. Synopsys DesignWare also blend in a more complex business IP (no extra charge) Currently there are: 8051 micro-controller, PCI, PCI-X, USB2.0, MemoryBIST, AMBA SoC structural simulation, AMBA bus controller IP modules such as
Platform: | Size: 420864 | Author: 宝龙富乐 | Hits:

[VHDL-FPGA-Verilog国产FPGA参考设计IPCORE_UART_example_M5&M7

Description: 国产FPGA的UART参考设计IPCORE源代码。 The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface. Support programmable baud rate Synchronous mode, fixed baud rate 5-bi(The IP provides two kinds of simplified interface connected to EMIF bus and AHB bus for communication with 8051 core and ARM core.The two kinds of interface are full-duplex serial communication interface.)
Platform: | Size: 3162112 | Author: 空空居士 | Hits:
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